User guide

Use the following data rates and configuration settings for PLL IP cores:
• Transceiver PLL Instance 0: ATX PLL with output clock frequency of 6.25 GHz
• Enable the Master CGB and bonding output clocks.
• Transceiver PLL instance 1: ATX PLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 2: ATX PLL with output clock frequency of 5.1625 GHz
• Transceiver PLL instance 3: ATX PLL with output clock frequency of 4.9 GHz
• Transceiver PLL instance 4: fPLL with output clock frequency of 0.625 GHz
• Select the Use as Transceiver PLL option.
• Transceiver PLL instance 5: fPLL with output clock frequency of 2.5 GHz
• Select Enable PCIe clock output port option.
• Select Use as Transceiver PLL option.
• Set Protocol Mode to PCIe Gen2.
• Select the Use as Core PLL option
• Set the Desired frequency to 500 MHz with a phase shift of 0 ps.
• Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz
• Enable Master CGB and bonding output clocks.
• Select Enable PCIe clock switch interface option.
• Set Number of Auxiliary MCGB Clock Input ports to 1.
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Mix and Match Example
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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