User guide

Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
1000BASE-X Gigabit
Ethernet
Native PHY IP Standard GbE GIGE - 1.25 Gbps
1000BASE-X Gigabit
Ethernet with 1588
Native PHY IP Standard GbE 1588 GIGE - 1.25 Gbps 1588
10GBASE-R Native PHY IP Enhanced 10GBASE-R 10GBASE-R
10GBASE-R Low Latency Native PHY IP Enhanced 10GBASE-R 10GBASE-R Low Latency
10GBASE-R 1588 Native PHY IP Enhanced 10GBASE-R
1588
10GBASE-R 1588
10GBASE-R with KR FEC Native PHY IP Enhanced 10GBASE-R w/
KR FEC
10GBASE-R w/KR FEC
10GBASE-KR and
1000BASE-X
1G/10GbE and
10GBASE-KR
PHY IP
(18)
Standard and
Enhanced
Not applicable
BackPlane_wo_1588
LineSide (optical)
LineSide(optical)_1588
40GBASE-R/100GBASE-R Native PHY IP Enhanced Basic (Enhanced
PCS)
Low Latency Enhanced
PCS
(23) (21)
40GBASE-R with FEC/
40GBASE-KR4
(19)
Native PHY IP Enhanced Basic w/KR FEC User created
100GBASE-R via CAUI-4/
CPPI-4/BP-4
Native PHY IP Enhanced PCS
(low latency
mode) PCS
Direct
Basic (Enhanced
PCS) / PCS
Direct
Low Latency GT
(23)
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
UG-01143
2015.05.11
Arria 10 Transceiver Protocols and PHY IP Support
2-11
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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