User guide

Implementing Multi-Channel xN Non-Bonded Configuration
Using the xN non-bonded configuration reduces the number of PLL resources and the reference clock
sources used.
Figure 3-21: PHY IP Core and PLL IP Core Connection for Multi-Channel xN Non-Bonded Configuration
In this example, the same PLL is used to drive 10 channels across two transceiver banks.
Transceiver PLL
Instance (5 GHz)
ATX PLL
Native PHY Instance
(10 CH Non-Bonded 10 Gbps)
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
TX Channel
Master
CGB
xN
Legend:
TX channels placed in the adjacent transceiver bank.
TX channels placed in the same transceiver bank.
x1
x6
Steps to implement a multi-channel xN non-bonded configuration
1. You can use either the ATX PLL or fPLL for multi-channel xN non-bonded configuration.
• Refer to Instantiating the ATX PLL IP Core on page 3-5 or Instantiating the fPLL IP Core on
page 3-15 for detailed steps.
• Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for
this example.
2. Configure the PLL IP core using the IP Parameter Editor. Enable Include Master Clock Generation
Block .
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP TX Channel bonding mode to Non-Bonded .
• Set the number of channels as per your design requirement. In this example, the number of
channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
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Implementing Multi-Channel xN Non-Bonded Configuration
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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