User guide

Related Information
Quartus II Incremental Compilation for Hierarchical and Team-Based Design
For more information about compilation details.
Verify Design Functionality
Simulate your design to verify the functionality of your design. For more details, refer to Simulating the
Native Transceiver PHY IP Core section.
Related Information
• Simulating the Transceiver Native PHY IP Core on page 2-322
• Quartus II Handbook - Volume 3: Verification
Information about design simulation and verification.
Arria 10 Transceiver Protocols and PHY IP Support
Table 2-1: Arria 10 Transceiver Protocols and PHY IP Support
Protocol Transceiver IP PCS Support Transceiver
Configuration
Rule
(15)
Protocol Preset
(16)
PCIe Gen3 x1, x2, x4, x8 Native PHY IP
(PIPE)
(17)
Standard and
Gen3
Gen3 PIPE
PCIe PIPE Gen3 x1
PCIe PIPE Gen3 x8
PCIe Gen2 x1, x2, x4, x8 Native PHY IP
(PIPE)
(17)
Standard Gen2 PIPE
PCIe PIPE Gen2 x1
PCIe PIPE Gen2 x8
PCIe Gen1 x1, x2, x4, x8 Native PHY IP
(PIPE)
(17)
Standard Gen1 PIPE User created
(15)
For more information about Transceiver Configuration Rules, refer to Using the Arria 10 Transceiver
Native PHY IP Core on page 2-17.
(16)
For more information about Protocol Presets, refer to Using the Arria 10 Transceiver Native PHY IP Core
on page 2-17.
(17)
Hard IP for PCI Express is also available as a separate IP core.
(18)
The 1G/10GbE and 10GBASE-KR PHY IP core includes the necessary soft IP for link training, auto speed
negotiation, and sequencer functions.
(19)
Needs a user created IP for link training, auto speed negotiation, and sequencer functions.
(20)
A Transmit PCS soft bonding logic required for multi-lane bonding configuration and a Receive PCS multi-
lane deskew control logic is provided in the design example.
(21)
To implement 40GBASE-R/100GBASE-R using the Low Latency Enhanced PCS preset, change the number
of data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(22)
To implement 100GBASE-R via CAUI using the Low Latency Enhanced PCS preset, change the number of
data channels to 10 and select appropriate PCS-FPGA Fabric and PCS-PMA width.
(23)
Low Latency GT protocol preset requires some modification to implement OTU-4 (100G) via OTL4.4/CEI-
28G-VSR.
2-10
Verify Design Functionality
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
Send Feedback