User guide

Figure 3-12: FPGA Fabric - Transceiver Interface Clocking
Input Reference Clock
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
/2, /4
/2, /4
Parallel and Serial Clocks
Clock Divider
rx_pma_div_clkout
Serial Clock
Clock Generation Block (CGB)
tx_coreclkin
rx_coreclkin
rx_clkout or
tx_clkout
Parallel Clock
(Recovered)
Parallel Clock
(From Clock
Divider)
tx_clkout
tx_clkout
tx_clkout
rx_clkout
PRBS
Verifier
tx_pma_div_clkout
CMU PLL /
ATX PLL /
CTX PLL
/66
/40
/33
/2
Serializer
tx_pma_div_clkout
Serial Clock
(from CGB)
tx_clkout
/66
/40
/33
/2
Deserializer
rx_pma_div_clkout
rx_clkout
Parallel Clock
Serial Clock
Parallel and Serial Clocks
The divided versions of the tx_clkout and rx_clkout are available as tx_pma_div_clkout and
rx_pma_div_clkout, respectively.
The output frequency of tx_pma_div_clkout and rx_pma_div_clkout can be one of the following:
• A divided down version of the tx_clkout or rx_clkout respectively, where divide by 1 and divide by
2 ratios are available.
• A divided down version of the serializer clock where divide by 33, 40, and 66 ratios are available.
3-40
FPGA Fabric-Transceiver Interface Clocking
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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