User guide

Figure 3-11: Clock Generation Block and Clock Network
The local clock for each transceiver channel can be sourced from either the local CGB via the x1 network,
or the master CGB via the x6/xN network. For example, as shown by the red highlighted path, the ATX
PLL 1 drives the x1 network which in turn drives the master CGB. The master CGB then drives the x6
clock network which routes the clocks to the local channels. As shown by the blue highlighted path, the
ATX PLL 0 can also drive the x1 clock network which can directly feed a channel's local CGB. In this case,
the low speed parallel clock is generated by the local CGB.
CMU or CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CMU or CDR
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
Master
CGB1
Master
CGB0
xN
Up
x1
Network
ATX PLL 1
fPLL 1
fPLL 0
ATX PLL 0
Transceiver
Bank
xN
Down
x6
Top
x6
Bottom
3-38
Clock Generation Block
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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