User guide

Connect the PHY IP to the PLL IP and Reset Controller
Connect the PHY IP, PLL IP, and the reset controller. Write the top level module to connect all the IP
blocks.
All of the I/O ports for each IP, can be seen in the <phy instance name>.v file or <phy instance name>.vhd,
and in the <phy_instance_name>_bb.v file.
For more information about description of the ports, refer to the ports tables in the PLL IP and Reset
Controller, Using the Transceiver Native PHY IP Core, and Resetting Transceiver Channels chapters.
Related Information
• Enhanced PCS Ports on page 2-54
• Standard PCS Ports on page 2-68
• Resetting Transceiver Channels on page 4-1
• Using the Arria 10 Transceiver Native PHY IP Core on page 2-17
• PLLs and Clock Networks on page 3-1
Connect Datapath
Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data
generator / analyzer or a frame generator / analyzer.
Make Analog Parameter Settings
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus II
Settings File.
After verifying your design functionality, make pin assignments and PMA analog parameter settings for
the transceiver pins.
1. Assign FPGA pins to all the transceiver and reference clock I/O pins. For more details, refer to the
Arria 10 Pin Connection Guidelines.
2. Set the analog parameters to the transmitter, receiver, and reference clock pins using the Assignment
Editor.
All of the pin assignments and analog parameters set using the Pin Planner and the Assignment
Editor are saved in the <top_level_project_name>.qsf file. You can also directly modify the Quartus
Settings file (.qsf) to set PMA analog parameters.
Related Information
• Analog Parameter Settings on page 8-1
• Arria 10 Pin Connection Guidelines
Compile the Design
To compile the transceiver design, add the <phy_instancename>.qip files for all the IP blocks generated
using the IP Catalog to the Quartus II project library. You can alternatively add the .qsys and .qip variants
of the IP cores.
Note:
If you add both the .qsys and the .qip file into the Quartus II project, the software generates an
error.
UG-01143
2015.05.11
Connect the PHY IP to the PLL IP and Reset Controller
2-9
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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