User guide

Receiver Input Pins........................................................................................................................3-29
PLL Cascading as an Input Reference Clock Source.................................................................3-30
Reference Clock Network.............................................................................................................3-30
Global Clock or Core Clock as an Input Reference Clock.......................................................3-30
Transmitter Clock Network..................................................................................................................... 3-30
x1 Clock Lines................................................................................................................................ 3-31
x6 Clock Lines................................................................................................................................ 3-32
xN Clock Lines............................................................................................................................... 3-33
GT Clock Lines...............................................................................................................................3-35
Clock Generation Block............................................................................................................................3-36
FPGA Fabric-Transceiver Interface Clocking....................................................................................... 3-39
Transmitter Data Path Interface Clocking.............................................................................................3-41
Receiver Data Path Interface Clocking...................................................................................................3-42
Channel Bonding.......................................................................................................................................3-44
PMA Bonding.................................................................................................................................3-44
PMA and PCS Bonding.................................................................................................................3-45
Selecting Channel Bonding Schemes.......................................................................................... 3-47
Skew Calculations.......................................................................................................................... 3-47
PLL Feedback and Cascading Clock Network.......................................................................................3-47
Using PLLs and Clock Networks.............................................................................................................3-49
Non-bonded Configurations........................................................................................................3-49
Bonded Configurations.................................................................................................................3-53
Implementing PLL Cascading......................................................................................................3-57
Mix and Match Example...............................................................................................................3-59
Timing Closure Recommendations............................................................................................ 3-62
Resetting Transceiver Channels..........................................................................4-1
When Is Reset Required? ...........................................................................................................................4-2
How Do I Reset?...........................................................................................................................................4-2
Recommended Reset Sequence......................................................................................................4-3
Transceiver Blocks Affected by Reset and Powerdown Signals.................................................4-8
Using the Altera Transceiver PHY Reset Controller.............................................................................. 4-9
Parameterizing the Transceiver PHY Reset Controller IP.......................................................4-11
Transceiver PHY Reset Controller Parameters......................................................................... 4-11
Transceiver PHY Reset Controller Interfaces............................................................................4-13
Transceiver PHY Reset Controller Resource Utilization.........................................................4-17
Using a User-Coded Reset Controller.................................................................................................... 4-18
User-Coded Reset Controller Signals..........................................................................................4-18
Combining Status or PLL Lock Signals ................................................................................................. 4-19
Timing Constraints for Bonded PCS and PMA Channels...................................................................4-20
Arria 10 Transceiver PHY Architecture............................................................. 5-1
Arria 10 PMA Architecture........................................................................................................................5-1
Transmitter.......................................................................................................................................5-1
Receiver............................................................................................................................................. 5-4
Loopback.........................................................................................................................................5-16
Arria 10 Enhanced PCS Architecture..................................................................................................... 5-18
TOC-4
Arria 10 Transceiver PHY Overview
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