User guide

configurations, the low speed parallel clock output of the master CGB is used, and the local CGB within
each channel is bypassed. For non-bonded configurations, the master CGB provides a high speed serial
clock output to each channel.
Figure 3-9: xN Clock Network
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
x6
Top
Master
CGB1
Master
CGB0
xN Up xN Down
x6
Bottom
xN Up
xN Down
CMU or CDR
CMU or CDR
The maximum channel span of a xN clock network is two transceiver banks above and two transceiver
banks below the bank that contains the driving PLL and the master CGB. A maximum of 30 channels can
be used in a single bonded or non-bonded xN group.
The maximum data rate supported by the xN clock network while driving channels in either the bonded
or non-bonded mode depends on the voltage used to drive the transceiver banks. All transceiver banks in
3-34
xN Clock Lines
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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