User guide

x1 Clock Lines
The x1 clock lines route the high speed serial clock output of a PLL to any channel within a transceiver
bank. The low speed parallel clock is then generated by that particular channel's local clock generation
block (CGB). Non-bonded channel configurations use the x1 clock network.
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel
1 and 4 when used as a CMU PLL) within a transceiver bank.
The x1 clock lines are also used to drive the master CGB in bonded channel configurations. Either one of
the master CGBs in each transceiver bank can drive the x6 clock lines for bonded channel configurations.
The master CGB can only be driven by the ATX PLL or the fPLL. Because the CMU PLLs cannot drive the
master CGB,the CMU PLLs cannot be used for bonding purposes.
UG-01143
2015.05.11
x1 Clock Lines
3-31
PLLs and Clock Networks
Altera Corporation
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