User guide

• fPLL IP Core on page 3-15
• CMU PLL IP Core on page 3-24
• Using PLLs and Clock Networks on page 3-49
Generate the PLL IP Core
After configuring the PLL IP, complete the following steps to generate the PLL IP.
1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware description language
you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation targets if you want to
clear any previous IP generation files from the selected output directory.
5. Click Generate.
The Quartus
®
II software generates a <pll ip instance name> folder, <pll ip instance name>_sim folder,
<pll ip instance name>.qip file, <pll ip instance name>.qsys, and <pll ip instance name>.v file or <pll ip
instance name>.vhd file. The <pll ip instance name>.v file is the top level design file for the PLL IP and is
placed in the <pll ip instance name>/ synth folder. The other folders contain lower level design files used
for simulation and compilation.
Related Information
IP Core File Locations on page 2-75
Reset Controller
There are two methods to reset the transceivers in Arria 10 devices:
• Use the Altera Transceiver PHY Reset Controller IP Core.
• Create your own reset controller that follows the recommended reset sequence.
Related Information
Resetting Transceiver Channels on page 4-1
Create Reconfiguration Logic
Dynamic reconfiguration is the ability to dynamically modify the transceiver channels and PLL settings
during device operation. To support dynamic reconfiguration, your design must include an Avalon
master that can access the dynamic reconfiguration registers using the Avalon-MM interface.
The Avalon-MM master enables PCS dynamic switching, PLL and channel reconfiguration. You can
dynamically adjust the PMA parameters, such as differential output voltage swing (Vod), and pre-
emphasis settings. This adjustment can be done by writing to the Avalon-MM reconfiguration registers
through the user generated Avalon-MM master.
For detailed information on dynamic reconfiguration, refer to Reconfiguration Interface and Dynamic
Reconfiguration chapter.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
2-8
Generate the PLL IP Core
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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