User guide

Table 3-15: CMU PLL IP Ports
Port Range Clock Domain Description
pll_powerdown input Asynchronous Resets the PLL when asserted
high.
pll_refclk0 input N/A Reference clock input port 0.
There are 5 reference clock input
ports. The number of reference
clock ports available depends on
the Number of PLL reference
clocks parameter.
pll_refclk1 input N/A Reference clock input port 1.
pll_refclk2 input N/A Reference clock input port 2.
pll_refclk3 input N/A Reference clock input port 3.
pll_refclk4 input N/A Reference clock input port 4.
tx_serial_clk output N/A High speed serial clock output
port for GX channels. Represents
the x1 clock network.
pll_locked output Asynchronous Active high status signal which
indicates if PLL is locked.
reconfig_clk0 input N/A Optional Avalon interface clock.
Used for PLL reconfiguration.
The reconfiguration ports appear
only if the Enable Reconfigura‐
tion parameter is selected in the
PLL IP GUI. When this
parameter is not selected, the
ports are set to OFF internally.
reconfig_reset0 input reconfig_clk0 Used to reset the Avalon
interface.
reconfig_write0 input reconfig_clk0 Active high write enable signal.
reconfig_read0 input reconfig_clk0 Active high read enable signal.
3-26
CMU PLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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