User guide

Table 3-13: CMU PLL—Dynamic Reconfiguration
Parameters Range Description
Enable dynamic reconfigura‐
tion
On/Off Enables the PLL reconfiguration interface. Enables
the simulation models and adds more ports for
reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off When you turn this option On, the transceiver PLL
IP includes an embedded Altera Debug Master
Endpoint that connects internally to the Avalon-
MM slave interface for dynamic reconfiguration.
The ADME can access the reconfiguration space of
the transceiver. It can perform certain test and
debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Enable capability registers On/Off Enables capability registers that provide high- level
information about the CMU PLL's configuration.
Set user-defined IP identifier Sets a user-defined numeric identifier that can be
read from the user_identifier offset when the
capability registers are enabled.
Enable control and status
registers
On/Off Enables soft registers for reading status signals and
writing control signals on the PLL interface through
the embedded debug logic.
Configuration file prefix Enter the prefix name for the configuration files to
be generated.
Generate SystemVerilog
package file
On/Off Generates a SystemVerilog package file containing
all relevant parameters used by the PLL.
Generate C header file On/Off Generates a C header file containing all relevant
parameters used by the PLL.
Generate MIF (Memory
Initialize File)
On/Off Generates a MIF file that contains the current
configuration.
Use this option for reconfiguration purposes in
order to switch between different PLL configura‐
tions.
Table 3-14: CMU PLL—Generation Options
Parameters Range Description
Generate parameter documen‐
tation file
On/Off Generates a .csv file which contains the descrip‐
tions of all CMU PLL parameters and values.
UG-01143
2015.05.11
CMU PLL IP Core
3-25
PLLs and Clock Networks
Altera Corporation
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