User guide

CMU PLL IP Core
Table 3-12: CMU PLL Parameters and Settings
Parameters Range Description
Message level for rule violations Error
Warning
Specifies the messaging level to use for parameter
rule violations.
• Error - Causes all rule violations to prevent IP
generation.
• Warning - Displays all rule violations as
warnings and will allow IP generation in spite of
violations.
Bandwidth Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the
expense of decreased jitter rejection.
Number of PLL reference
clocks
1 to 5 Specifies the number of input reference clocks for
the CMU PLL.
You can use this parameter for data rate reconfigu‐
ration.
Selected reference clock source 0 to 4 Specifies the initially selected reference clock input
to the CMU PLL.
TX PLL Protocol mode BASIC
PCIE
This parameter governs the rules for correct
protocol specific settings. Certain features of the
PLL are only available for specific protocol configu‐
ration rules. This parameter is not a preset .
You must set all the other parameters for your
protocol.
PLL reference clock frequency 50 MHz to 800
MHz
Selects the input reference clock frequency for the
PLL.
PLL output frequency 437.5 MHz to
8.7 GHz
Specify the target output frequency for the PLL.
Multiply factor (M-Counter) Read only Displays the M-multiplier value.
Divide factor (N-Counter) Read only Displays the N-counter value.
Divide factor (L-Counter) Read only Displays the L-counter value.
3-24
CMU PLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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