User guide
The PFD output is used by the charge pump and loop filter to generate a control voltage for the VCO. The
charge pump translates the "Up"/"Down" pulses from the PFD into current pulses. The current pulses are
filtered through a low pass filter into a control voltage which drives the VCO frequency.
Voltage Controlled Oscillator (VCO)
The CMU PLL has a ring oscillator based VCO. The fundamental VCO frequency range is from 4 GHz to
14 GHz. Lower frequencies can be generated using the PFD and M counter settings.
L Counter
The L counter divides the differential clocks generated by the CMU PLL. The division factors supported
are 1, 2, 4, and 8.
M Counter
The M counter is used in the PFD's feedback path. The output of the L counter is connected to the M
counter. The combined division ratios of the L counter and the M counter determine the overall division
factor in the PFD's feedback path.
The division factors supported are 8, 9, 10, 12, 15, 16, 18, 20, 24, 25, 30, 32, 36, 40, 48, 50, 60, 64, 72, 80, 96,
100, 120, 128, 160, and 200.
Lock Detector (LD)
The lock detector indicates when the CMU PLL is locked to the desired output's phase and frequency. The
lock detector XORs the "Up"/"Down" pulses and indicates when the M counter's output and N counter's
output are phase-aligned.
The reference clock (refclk) and feedback clock (fbclk) are sent to the PCS's ppm detector block. There
is a pre-divider to lower the frequency in case the frequency is too high.
Related Information
Calibration on page 7-1
Instantiating CMU PLL IP Core
The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in hardware. One
instance of the CMU PLL IP core represents one CMU PLL in hardware.
1. Open the Quartus II software.
2. Click Tools > IP Catalog.
3. In IP Catalog, under Library > Transceiver PLL , select Arria 10 Transceiver CMU PLL and click
Add.
4. In the New IP Instance Dialog Box, provide the IP instance name.
5. Select Arria 10 device family.
6. Select the appropriate device and click OK.
The CMU PLL IP Parameter Editor window opens.
UG-01143
2015.05.11
Instantiating CMU PLL IP Core
3-23
PLLs and Clock Networks
Altera Corporation
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