User guide

Figure 3-4: CMU PLL Block Diagram
VCO
PFD
CP +
LF
M Counter
VCO
Calibration
N Counter
L Counter
Lock to
Reference
Controller
User Control
(LTR/LTD)
Lock to Reference
PLL Lock Status
Output
Lock
Detector
Reference clock network
Up
Down
Input reference
clock
refclk
fbclk
Receiver input pin
Refclk
Multiplexer
Input Reference Clock
The input reference clock for a CMU PLL can be sourced from either the reference clock network or a
receiver input pin. The input reference clock is a differential signal. The input reference clock must be
stable and free-running at device power-up for proper PLL operation. If the reference clock is not
available at device power-up, then you must recalibrate the PLL when the reference clock is available.
Refer to the Calibration section for details about PLL calibration and the CLKUSR clock requirement.
Note:
The CMU PLL calibration is clocked by the CLKUSR clock which must be stable and available for
calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.
Reference Clock Multiplexer (Refclk Mux)
The refclk mux selects the input reference clock to the PLL from the various reference clock sources
available.
N Counter
The N counter divides the refclk mux's output. The N counter division helps lower the loop bandwidth or
reduce the frequency to within the phase frequency detector's (PFD) operating range. Possible divide
ratios are 1 (bypass), 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock (refclk) signal at the output of the N counter block and the feedback clock (fbclk)
signal at the output of the M counter block is supplied as an input to the PFD. The PFD output is
proportional to the phase difference between the two inputs. It aligns the input reference clock (refclk)
to the feedback clock (fbclk). The PFD generates an "Up" signal when the reference clock's falling edge
occurs before the feedback clock's falling edge. Conversely, the PFD generates a "Down" signal when
feedback clock's falling edge occurs before the reference clock's falling edge.
Charge Pump and Loop Filter (CP + LF)
3-22
CMU PLL
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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