User guide

Port Range Clock Domain Description
reconfig_readdata0[31:0] output reconfig_clk0 32-bit data bus. Carries the
read data from the specified
address.
reconfig_waitrequest0 output reconfig_clk0 Indicates when the Avalon
interface signal is busy. When
asserted, all inputs must be
held constant.
pll_cal_busy output Asynchronous Status signal which is asserted
high when PLL calibration is in
progress.
Perform logical OR with this
signal and the tx_cal_busy
port on the reset controller IP.
mcgb_rst input Asynchronous Master CGB reset control.
If PLL feedback compensation
bonding mode is used, deassert
this reset at the same time as
pll_powerdown .
If PLL feedback compensation
bonding is not being used,
then this port can be
deasserted after pll_
powerdown is deasserted, but
before tx_analogreset is de-
asserted. Alternatively, this
port can be deasserted at the
same time as pll_powerdown.
mcgb_aux_clk0 input N/A Used for PCIe to switch
between fPLL/ATX PLL during
link speed negotiation.
tx_bonding_clocks[5:0] Output N/A Optional 6-bit bus which
carries the low speed parallel
clock outputs from the Master
CGB.
Used for channel bonding, and
represents the x6/xN clock
network.
mcgb_serial_clk Output N/A High speed serial clock output
for x6/xN non-bonded
configurations.
3-20
fPLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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