User guide

Parameter Range Description
Enable Altera Debug Master
Endpoint
On/Off When you turn this option ON, the transceiver PLL
IP core includes an embedded Altera Debug Master
Endpoint (ADME) that connects internally to the
Avalon-MM slave interface for dynamic reconfigu‐
ration. The ADME can access the reconfiguration
space of the transceiver. It can perform certain test
and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Enable capability registers
On/Off Enables capability registers that provide high-level
information about the fPLL's configuration.
Set user-defined IP identifier
Sets a user-defined numeric identifier that can be
read from the user_identifier offset when the
capability registers are enabled.
Enable control and status
registers
On/Off Enables soft registers for reading status signals and
writing control signals on the PLL interface through
the embedded debug logic.
Configuration file prefix Enter the prefix name for the configuration files to
be generated.
Generate SystemVerilog
package file
On/Off Generates a SystemVerilog package file containing
all relevant parameters used by the PLL.
Generate C header file On/Off Generates a C header file containing all relevant
parameters used by the PLL.
Generate MIF (Memory
Initialize File)
On/Off Generates a MIF file that contains the current
configuration.
Use this option for reconfiguration purposes in
order to switch between different PLL configura‐
tions.
Table 3-10: fPLL - Generation Options
Parameter Range Description
Generates parameter documen‐
tation file
On/Off Generates a .csv file that contains descriptions of all
the fPLL parameters and values.
Table 3-11: fPLL IP Ports
Port Range Clock Domain Description
pll_powerdown input Asynchronous Resets the PLL when asserted
high.
3-18
fPLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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