User guide

Parameters Range Description
Enable fractional mode On/Off Enables the fractional frequency mode.
This enables the PLL to output frequencies which
are not integral multiples of the input reference
clock.
Enable manual counter
configurations
On/Off Selecting this option allows you to manually specify
M, N, C and L counter values.
Enable cascade input port On/Off Enables the ATX to fPLL cascade clock input port.
This port should only be used to drive the fPLL
from the cascade output clock port of an ATX PLL.
Desired Reference clock
frequency
27 MHz to 800
MHz
Specifies the desired PLL input reference clock
frequency.
Actual reference clock
frequency
Read-only Displays the actual PLL input reference clock
frequency.
Number of PLL reference clocks 1 to 5 Specify the number of input reference clocks for the
FPLL.
Bandwidth Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the
expense of decreased jitter rejection.
Operation mode Direct
Feedback
compensation
bonding
Specifies the feedback operation mode for the fPLL.
Multiply factor (M-counter) 1 to 255 Specifies the multiply factor (M-counter)
Divide factor (N-counter) 1 to 63 Specifies the divide factor (N-counter)
Divide factor (L-counter) 1 to 63 Specifies the divide factor (L-counter)
Divide factor (K-counter) User defined Specifies the divide factor (K-counter)
PLL output frequency Read-only Displays the target output frequency for the PLL.
PLL Datarate Read-only Displays the PLL datarate.
3-16
fPLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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