User guide

Dynamic Phase Shift
The dynamic phase shift block allows you to adjust the phase of the M and C counters in user mode. In
fractional mode, dynamic phase shift is only available for the C counters. Adjusting the M counter may
cause the fPLL to lose lock.
Latency
The fPLL contains a 1 ns delay with 50 ps resolution on each C, M, and N counter. In addition, there is a 7
ns delay with 1 ns resolution on both the reference clock and feedback clock paths. The C and M counters
can be configured to select any VCO phase and a delay of up to 128 clock cycles. The selected VCO phase
can be changed dynamically. The M counter's phase cannot be changed in fractional mode.
Related Information
Calibration on page 7-1
Instantiating the fPLL IP Core
The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One instance of the fPLL
IP core represents one fPLL in the hardware.
1. Open the Quartus II software.
2. Click Tools > IP Catalog.
3. In IP Catalog, under Library > Transceiver PLL , select Arria 10 Transceiver fPLL IP core and click
Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The fPLL IP core Parameter Editor window opens.
fPLL IP Core
Table 3-7: fPLL IP Core Configuration Options, Parameters, and Settings
Parameters Range Description
fPLL Mode Core
Cascade Source
Transceiver
Specifies the fPLL mode of operation.
Select Core to use fPLL as a general purpose PLL to
drive the FPGA core clock network.
Select Cascade Source to connect an fPLL to
another PLL as a cascading source.
Select Transceiver to use an fPLL as a transmit PLL
for the transceiver block.
Protocol Mode Basic
PCIe Gen1
PCIe Gen2
PCIe Gen3
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all
parameters for your protocol.
UG-01143
2015.05.11
Instantiating the fPLL IP Core
3-15
PLLs and Clock Networks
Altera Corporation
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