User guide

Port Direction Clock Domain Description
pll_locked Output Asynchronous Active high status signal which
indicates if the PLL is locked.
pll_pcie_clk Output N/A Used for PCIe.
(49)
reconfig_clk0 Input N/A Optional Avalon interface clock.
Used for PLL reconfiguration.
The reconfiguration ports appear
only if the Enable Reconfigura‐
tion parameter is selected in the
PLL IP GUI. When this
parameter is not selected, the
ports are set to OFF internally.
reconfig_reset0 Input reconfig_clk0 Used to reset the Avalon
interface.
reconfig_write0 Input reconfig_clk0 Active high write enable signal.
reconfig_read0 Input reconfig_clk0 Active high read enable signal.
reconfig_address0[9:0] Input reconfig_clk0 10-bit address bus used to
specify address to be accessed for
both read and write operations.
reconfig_writedata0[31:0] Input reconfig_clk0 32-bit data bus. Carries the write
data to the specified address.
reconfig_readdata0[31:0] Output reconfig_clk0 32-bit data bus. Carries the read
data from the specified address.
reconfig_waitrequest0 Output reconfig_clk0 Indicates when the Avalon
interface signal is busy. When
asserted, all inputs must be held
constant.
pll_cal_busy Output Asynchronous Status signal which is asserted
high when PLL calibration is in
progress.
OR this signal with tx_cal_busy
port before connecting to the
reset controller IP.
(49)
Connect this clock to hclk in PCIe applications.
UG-01143
2015.05.11
ATX PLL IP Core
3-11
PLLs and Clock Networks
Altera Corporation
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