User guide

Parameter Range Description
Generate SystemVerilog
package file
On/Off Generates a SystemVerilog package file containing
all relevant parameters used by the PLL.
Generate C header file On/Off Generates a C header file containing all relevant
parameters used by the PLL.
Generate MIF (Memory
Initialize File)
On/Off Generates a MIF file which contains the current
configuration.
Use this option for reconfiguration purposes in
order to switch between different PLL configura‐
tions.
Table 3-5: ATX PLL—Generation Options
Parameter Range Description
Generate parameter documen‐
tation file
On/Off Generates a .csv file which contains descriptions of
ATX PLL IP parameters and values.
Table 3-6: ATX PLL IP Ports
Port Direction Clock Domain Description
pll_powerdown Input Asynchronous Resets the PLL when asserted
high.
pll_refclk0 Input N/A Reference clock input port 0.
There are a total of five reference
clock input ports. The number of
reference clock ports available
depends on the Number of PLL
reference clocks parameter.
pll_refclk1 Input N/A Reference clock input port 1.
pll_refclk2 Input N/A Reference clock input port 2.
pll_refclk3 Input N/A Reference clock input port 3.
pll_refclk4 Input N/A Reference clock input port 4.
tx_serial_clk Output N/A High speed serial clock output
port for GX channels. Represents
the x1 clock network.
tx_serial_clk_gt Output N/A High speed serial clock output
port for GT channels. Represents
the GT clock network.
3-10
ATX PLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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