User guide

Parameter Range Description
Enable bonding clock output
ports
On/Off Enables the tx_bonding_clocks output ports of the
master CGB used for channel bonding.
This option should be turned ON for bonded
designs.
Enable feedback compensation
bonding
On/Off Enables this setting when using feedback compensa‐
tion bonding. For more details about feedback
compensation bonding, refer to the PLL Feedback
Compensation Bonding section later in the
document.
PMA interface width 8, 10, 16, 20, 32,
40, 64
Specifies PMA-PCS interface width.
Match this value with the PMA interface width
selected for the Native PHY IP core. You must
select a proper value for generating bonding clocks
for the Native PHY IP core.
Table 3-4: ATX PLL—Dynamic Reconfiguration
Parameter Range Description
Enable reconfiguration On/Off Enables the PLL reconfiguration interface. Enables
the simulation models and adds Avalon compliant
ports for reconfiguration.
Enable Altera Debug Master
Endpoint
On/Off When you turn on this option, the Transceiver PLL
IP includes an embedded Altera Debug Master
Endpoint (ADME) that connects internally to the
Avalon-MM slave interface for dynamic reconfigu‐
ration. The ADME can access the reconfiguration
space of the transceiver. It can perform certain test
and debug functions via JTAG using the System
Console. Refer to the Reconfiguration Interface and
Dynamic Reconfiguration chapter for more details.
Enable capability registers On/Off Enables capability registers that provide high-level
information about the ATX PLL's configuration.
Set user-defined IP identifier User-defined Sets a user-defined numeric identifier that can be
read from the user_identifier offset when the
capability registers are enabled.
Enable control and status
registers
On/Off Enables soft registers for reading status signals and
writing control signals on the PLL interface through
the embedded debug logic.
Configuration file prefix Enter the prefix name for the configuration files to
be generated.
UG-01143
2015.05.11
ATX PLL IP Core
3-9
PLLs and Clock Networks
Altera Corporation
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