User guide

Parameter Range Description
PLL integer reference clock
frequency
User-defined Specifies the reference clock frequency for the ATX
PLL in fractional mode. This parameter is only
applicable for the ATX PLL in fractional mode.
When you enable the fractional mode for ATX PLL,
this parameter replaces the PLL reference clock
frequency parameter in the Parameter Editor
window.
Multiply factor (M-Counter) Read only Displays the M-counter value.
Divide factor (N-Counter) Read only Displays the N-counter value.
Divide factor (L-Counter) Read only Displays the L-counter value.
Fractional multiply factor (K) Read only Displays the actual K-counter value. This parameter
is only available in fractional mode.
Table 3-3: ATX PLL—Master Clock Generation Block Parameters and Settings
Parameter Range Description
Include Master Clock
Generation Block
(48)
On/Off When enabled, includes a master CGB as a part of
the ATX PLL IP. The PLL output drives the Master
CGB.
This is used for x6/xN bonded and nonbonded
modes.
Clock division factor 1, 2, 4, 8 Divides the master CGB clock input before
generating bonding clocks.
Enable x6/xN non-bonded
high-speed clock output port
On/Off Enables the master CGB serial clock output port
used for x6/xN non-bonded modes.
Enable PCIe clock switch
interface
On/Off Enables the control signals for the PCIe clock switch
circuitry. Used for PCIe clock rate switching.
Number of auxiliary MCGB
clock input ports
0, 1 Auxiliary input is used to implement the PCIe Gen3
protocol.
MCGB input clock frequency Read only Displays the master CGB's input clock frequency.
MCGB output data rate. Read only Displays the master CGB's output data rate.
(48)
Manually enable the MCGB for bonding applications.
3-8
ATX PLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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