User guide

Parameter Range Description
Primary PLL clock output
buffer
GX clock output
buffer
GT clock output
buffer
Cascade Source
Specifies which PLL output is active initially.
• If GX is selected, turn ON "Enable PLL GX
clock output port".
• If GT is selected, turn ON “Enable PLL GT
clock output port".
• If Cascade Source is selected, turn ON "Enable
ATX to FPLL cascade clock output port".
Enable PLL GX clock output
port
(46)
On/Off Enables the GX output port which feeds x1 clock
lines.
You must select this parameter for PLL output
frequency less than 8 GHz, or if you intend to
reconfigure the PLL to a frequency below 8 GHz.
Turn ON this port if GX is selected in the "Primary
PLL clock output buffer".
Enable PLL GT clock output
port
(46)
On/Off Enables the GT output port which feeds dedicated
high speed clock lines.
You must select this parameter for PLL output
frequency greater than 8 GHz, or if you intend to
reconfigure the PLL to frequency above 8 GHz.
Turn ON this port if GT is selected in the "Primary
PLL clock output buffer" parameter.
Enable PCIe clock output port On/Off Exposes the pll_pcie_clk port used for PCI
Express.
The port should be connected to the pipe_hclk_
input port.
Enable ATX to FPLL cascade
clock output port
On/Off Enables the ATX to FPLL cascade clock output port.
PLL output frequency 437.5 MHz to
14.15 GHz
(47)
Use this parameter to specify the target output
frequency for the PLL.
PLL integer reference clock
frequency
61.5 MHz to 800
MHz
Selects the input reference clock frequency for the
PLL.
Enable fractional mode On/Off Enables the fractional frequency mode for ATX
PLL.
(46)
You can enable both the GX clock output port and the GT clock output port. However, only one port can be
in operation at any given time. You can switch between the two ports using PLL reconfiguration.
(47)
The maximum PLL output frequency supported by ATX PLL is 14.15 GHz for GT devices, and 8.7 GHz for
GX devices
UG-01143
2015.05.11
ATX PLL IP Core
3-7
PLLs and Clock Networks
Altera Corporation
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