User guide

1. Open the Quartus II software.
2. Click Tools > IP Catalog.
3. In IP Catalog, under Library > Transceiver PLL > , select Arria 10 Transceiver ATX PLL and click
Add.
4. In the New IP Instance dialog box, provide the IP instance name.
5. Select the Arria 10 device family.
6. Select the appropriate device and click OK.
The ATX PLL IP core Parameter Editor window opens.
ATX PLL IP Core
Table 3-2: ATX PLL Configuration Options, Parameters, and Settings
Parameter Range Description
Message level for rule violations Error
Warning
Specifies the messaging level to use for parameter
rule violations.
• Error—Causes all rule violations to prevent IP
generation.
• Warning—Displays all rule violations as
warnings and will allow IP generation in spite of
violations.
Protocol mode Basic
PCIe Gen1
PCIe Gen2
PCIe Gen3
Governs the internal setting rules for the VCO.
This parameter is not a preset. You must set all
other parameters for your protocol.
Bandwidth Low
Medium
High
Specifies the VCO bandwidth.
Higher bandwidth reduces PLL lock time, at the
expense of decreased jitter rejection.
Number of PLL reference
clocks
1 to 5 Specifies the number of input reference clocks for
the ATX PLL.
You can use this parameter for data rate reconfigu‐
ration.
Selected reference clock source 0 to 4 Specifies the initially selected reference clock input
to the ATX PLL.
3-6
ATX PLL IP Core
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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