User guide

Figure 3-2: ATX PLL Block Diagram
VCO 1
VCO 2
VCO 3
Lock
Detector
PFD
CP &
LF
Refclk
Multiplexer
2
2
/2
M Counter
Delta Sigma
Modulator (1)
N Counter
L Counter
Reference clock network
M Counter
Note: (1) The Delta Sigma Modulator is enaged only when the ATX PLL is used in fractional mode.
Receiver input pin
Output of another PLL
with PLL cascading
Dedicated reference clock pin
DownUp
Global clock or core clock
pll_locked
refclk
fbclk
Input reference
clock
Input Reference Clock
This is the dedicated input reference clock source for the PLL.
The input reference clock can be sourced from one of the following:
• Dedicated reference clock pin
• Reference clock network
• Receiver input pin
• Output of another PLL with PLL cascading
• Global clock or the core clock network
The input reference clock is a differential signal. Altera recommends using the dedicated reference clock
pin as the input reference clock source for the best jitter performance. The input reference clock must be
stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference
clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is
available.
Note:
The ATX PLL calibration is clocked by the CLKUSR clock which must be stable and available for
calibration to proceed. Refer to the Calibration section for more details about the CLKUSR clock.
Reference Clock Multiplexer
The reference clock (refclk) multiplexer selects the reference clock to the PLL from the various reference
clock sources available.
N Counter
The N counter divides the refclk mux's output. The division factors supported are 1, 2, 4, and 8.
Phase Frequency Detector (PFD)
The reference clock(refclk) signal at the output of the N counter block and the feedback clock (fbclk)
signal at the output of the M counter block are supplied as inputs to the PFD. The output of the PFD is
proportional to the phase difference between the refclk and fbclk inputs. It is used to align the refclk
3-4
ATX PLL
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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