User guide

Figure 3-1: Arria 10 PLLs and Clock Networks
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH5
Local CGB
CDR/CMU
CH4
Local CGB
CDR
CH3
fPLL
ATX
PLL
Master
CGB
Local CGB
CDR
CH2
Local CGB
CDR/CMU
CH1
Local CGB
CDR
CH0
fPLL
ATX
PLL
Master
CGB
x1 Clock Lines x6 Clock Lines xN Clock Lines
Transceiver
Bank
Transceiver
Bank
Related Information
• Channel Bonding on page 3-44
• Device Transceiver Layout on page 1-3
• Device Transceiver Layout on page 1-3
3-2
PLLs and Clock Networks
UG-01143
2015.05.11
Altera Corporation
PLLs and Clock Networks
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