User guide
PLLs and Clock Networks
3
2015.05.11
UG-01143
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This chapter describes the transceiver phase locked loops (PLLs), internal clocking architecture, and the
clocking options for the transceiver and the FPGA fabric interface.
As shown in the following figure, transceiver banks can have either three or six transceiver channels. For
every three channels, you get one advanced transmit (ATX) PLL, one fractional PLL (fPLL), and one
Master clock generation block (CGB). Refer to the Device Transceiver Layout section to identify which
devices have three channel transceiver banks.
The Arria 10 transceiver clocking architecture supports both bonded and non-bonded transceiver channel
configurations. Channel bonding is used to minimize the clock skew between multiple transceiver
channels. For Arria 10 transceivers, the term bonding can refer to PMA bonding as well as PMA and PCS
bonding. Refer to the Channel Bonding section for more details.
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