User guide

Related Information
• Using the Arria 10 Transceiver Native PHY IP Core on page 2-17
For information on Native PHY IP.
• Interlaken on page 2-76
• Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 on page 2-97
• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants on page 2-110
• 10GBASE-KR PHY IP Core on page 2-125
• 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core on page 2-163
• PCI Express (PIPE) on page 2-228
• CPRI on page 2-268
• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS on
page 2-279
• Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS on page
2-290
• Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels on page 2-
313
Generate the PHY IP Core
After configuring the PHY IP, complete the following steps to generate the PHY IP.
1. Click the Generate HDL button in the Parameter Editor window. The Generation dialog box opens.
2.
In Synthesis options, under Create HDL design for synthesis select Verilog or VHDL.
3. Select appropriate Simulation options depending on the choice of the hardware description language
you selected under Synthesis options.
4. In Output Directory, select Clear output directories for selected generation targets if you want to
clear any previous IP generation files from the selected output directory.
5. Click Generate.
The Quartus II software generates a <phy ip instance name> folder, <phy ip instance name>_sim folder,
<phy ip instance name>.qip file, <phy ip instance name>.qsys file, and <phy ip instance name>.v file or
<phy ip instance name>.vhd file. This <phy ip instance name>.v file is the top level design file for the PHY
IP and is placed in the <phy ip instance name>/synth folder. The other folders contain lower level design
files used for simulation and compilation.
Related Information
IP Core File Locations on page 2-75
Select the PLL IP Core
Arria 10 devices have three types of PLL IP cores:
• Advanced Transmit (ATX) PLL IP core.
• Fractional PLL (fPLL) IP core.
• Channel PLL / Clock Multiplier Unit (CMU) PLL IP core.
Select the appropriate PLL IP for your design. For additional details, refer to the PLLs and Clock Networks
chapter.
UG-01143
2015.05.11
Generate the PHY IP Core
2-5
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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