User guide

The Test Benches dialog box appears.
c. Click New.
d. Under Create new test bench settings, for Test bench name type the test bench name. For Top
level module in the test bench, type the top-level module name. These names should match the
actual test bench module names.
e. Select Use test bench to perform VHDL timing simulation and specify the name of your design
instance under Design instance name in test bench.
f. Under the Simulation period, turn on Run simulation until all vector stimuli are used.
g. Under Test bench and simulation files, select your test bench file from your folder. Click Add.
h. Click OK.
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How to Use NativeLink to Specify a ModelSim-Altera Simulation
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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