User guide

Parameter Range
Enable rx_pma_qpipulldn port (QPI) On / Off
Enable rx_is_lockedtodata port On / Off
Enable rx_is_lockedtoref port On / Off
Enable rx_set_locktodata and rx_set_
locktoref ports
On / Off
Enable rx_seriallpbken port On / Off
Enable PRBS verifier control and
status ports
On / Off
Table 2-191: PCS Direct Datapath Parameters
Parameter Range
PCS Direct interface width 8, 10, 16, 20, 32, 40, 64
Table 2-192: Dynamic Reconfiguration Parameters
Parameter Range
Enable dynamic reconfiguration
On / Off
Share reconfiguration interface
On / Off
Enable Altera Debug Master Endpoint
On / Off
Enable embedded debug
On / Off
Enable capability registers
On / Off
Set user-defined IP identifier number
Enable control and status registers
On / Off
Enable prbs soft accumulators
On / Off
Configuration file prefix text string
Generate SystemVerilog package file
On / Off
Generate C header file
On / Off
Generate MIF (Memory Initialization File)
On / Off
2-318
Native PHY IP Parameter Settings for PCS Direct Transceiver...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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