User guide

Parameter Range
Initial TX PLL clock input selection 0, 1, 2, 3
Enable tx_pma_clkout port On / Off
Enable tx_pma_div_clkout port On / Off
tx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable tx_pma_elecidle port On / Off
Enable tx_pma_qpipullup port (QPI) On / Off
Enable tx_pma_qpipulldn port (QPI) On / Off
Enable tx_pma_txdetectrx port (QPI) On / Off
Enable tx_pma_rxfound port (QPI) On / Off
Enable rx_seriallpbken port On / Off
Table 2-190: RX PMA Parameters
Parameter Range
Number of CDR reference clocks 1 to 5
Selected CDR reference clock 0 to 4
Selected CDR reference clock
frequency
Depends on the data rate
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual, triggered
DFE adaptation mode continuous, manual, disabled
Number of fixed dfe taps 3, 7
Enable rx_pma_clkout port On / Off
Enable rx_pma_div_clkout port On / Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66
Enable rx_pma_clkslip port On / Off
UG-01143
2015.05.11
Native PHY IP Parameter Settings for PCS Direct Transceiver...
2-317
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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