User guide

Parameter Range
TX FIFO mode
low_latency
register_fifo
fast_register
RX FIFO Mode
low_latency
register_fifo
Enable tx_std_pcfifo_full port On/Off
Enable tx_std_pcfifo_empty port On/Off
Enable rx_std_pcfifo_full port On/Off
Enable rx_std_pcfifo_empty port On/Off
TX byte serializer mode
Disabled
Serialize x2
Serialize x4
RX byte deserializer mode
Disabled
Deserialize x2
Deserialize x4
Enable TX 8B/10B encoder On/Off
Enable TX 8B/10B disparity control On/Off
Enable RX 8B/10B decoder On/Off
RX rate match FIFO mode
Disabled
Basic 10-bit PMA (for Basic with Rate
Match)
Basic 20-bit PMA (for Basic with Rate
Match)
RX rate match insert/delete -ve pattern (hex) User-defined value
RX rate match insert/delete +ve pattern (hex) User-defined value
Enable rx_std_rmfifo_full port On/Off
Enable rx_std_rmfifo_empty port On/Off
PCI Express Gen 3 rate match FIFO mode Bypass
Enable TX bit slip On/Off
Enable tx_std_bitslipboundarysel port On/Off
UG-01143
2015.05.11
Native PHY IP Parameter Settings for Basic, Basic with Rate Match...
2-311
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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