User guide

Parameter Range
Enable tx_pma_txdetectrx port (QPI) On/Off
Enable tx_pma_rxfound port (QPI) On/Off
Enable rx_seriallpbken port On/Off
Table 2-182: RX PMA Parameters
Parameter Range
Number of CDR reference clocks 1, 2, 3, 4, 5
Selected CDR reference clock 0, 1, 2, 3, 4
Selected CDR reference clock frequency
Legal range defined by Quartus II
software
PPM detector threshold 100, 300, 500, 1000
CTLE adaptation mode manual, triggered
DFE adaptation mode disabled
Number of fixed dfe taps 3, 7
Enable rx_pma_clkout port On/Off
Enable rx_pma_div_clkout port On/Off
rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 50, 66
Enable rx_pma_clkslip port On/Off
Enable rx_pma_qpipulldn port (QPI) On/Off
Enable rx_is_lockedtodata port On/Off
Enable rx_is_lockedtoref port On/Off
Enable rx_set_locktodata and rx_set_locktoref ports On/Off
Enable rx_seriallpbken port On/Off
Enable PRBS verifier control and status ports On/Off
Table 2-183: Standard PCS Parameters
Parameter Range
Standard PCS / PMA interface width 8, 10, 16, 20
FPGA fabric / Standard TX PCS interface width 8, 10, 16, 20, 32, 40
FPGA fabric / Standard RX PCS interface width 8, 10, 16, 20, 32, 40
Enable 'Standard PCS' low latency mode
On/Off
Off (for Basic with Rate Match)
2-310
Native PHY IP Parameter Settings for Basic, Basic with Rate Match...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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