User guide

Figure 2-137: Connection Guidelines for a Basic/Custom Design
reset
Pattern
Generator
Pattern
Checker
PLL IP
Reset
Controller
Arria 10
Transceiver
Native
PHY
tx_parallel_data
tx_datak
tx_clkout
pll_ref_clk
reset
tx_serial_clk
pll_locked
pll_powerdown
rx_ready
tx_ready
clk
reset
tx_digital_reset
tx_analog_reset
rx_digital_reset
rx_analog_reset
rx_is_lockedtoref
rx_is_lockedtodata
rx_parallel_data
rx_datak
rx_clkout
reconfig_clk
reconfig_reset
reconfig_write
tx_serial_data
rx_serial_data
For
Reconfiguration
rx_cdr_refclk
reconfig_read
reconfig_address
reconfig_writedata
reconfig_readdata
reconfig_waitrequest
cal_busy
8. Simulate your design to verify its functionality.
Related Information
• Arria 10 Standard PCS Architecture on page 5-37
For more information about Standard PCS architecture
• Arria 10 PMA Architecture on page 5-1
For more information about PMA architecture
• Using PLLs and Clock Networks on page 3-49
For more information about implementing PLLs and clocks
• PLLs on page 3-3
PLL architecture and implementation details
• Resetting Transceiver Channels on page 4-1
Reset controller general information and implementation details
• Standard PCS Ports on page 2-68
Port definitions for the Transceiver Native PHY Standard Datapath
Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
Table 2-180: General and Datapath Options Parameters
Parameter Range
Message level for rule violations
error
warning
2-308
Native PHY IP Parameter Settings for Basic, Basic with Rate Match...
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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