User guide

Figure 2-136: Signals and Ports of Native PHY IP for Basic, Basic with Rate Match Configurations
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digital_reset
tx_datak
tx_parallel_data[7:0]
tx_clkout
tx_datak
tx_parallel_data[7:0]
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
Reconfiguration
Registers
TX Standard PCS
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_coreclkin
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
unused_rx_parallel_data[113:0]
RX Standard PCS
Nios Hard
Calibration IP
TX PMA
Serializer
RX PMA
Deserializer CDR
tx_cal_busy
rx_cal_busy
tx_serial_data
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
Central/Local
Clock Divider
tx_serial_clk0 (from TX PLL)
tx_analog_reset
rx_analog_reset
rx_digital_reset
rx_datak
rx_parallel_data[7:0]
rx_clkout
rx_errdetect
rx_disperr
rx_runningdisp
rx_patterndetect
rx_syncstatus
rx_rmfifostatus (1)
10
10
Arria 10 Transceiver Native PHY
Note:
1. Only applies when using the Basic with Rate Match transceiver configuration rule.
5. Instantiate and configure your PLL.
6. Create a transceiver reset controller.
7. Connect the Native PHY IP to the PLL IP and the reset controller. Use the information in Native PHY
IP Parameter Settings for Basic, Basic with Rate Match Configurations to connect the ports.
UG-01143
2015.05.11
How to Implement the Basic, Basic with Rate Match Transceiver...
2-307
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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