User guide

Parameter Value Description
RX rate match insert/delete -ve pattern
(hex)
20 bits of data
specified as a
hexadecimal string
The first 10 bits correspond to the skip
pattern and the last 10 bits correspond
to the control pattern. The skip pattern
must have neutral disparity.
The rate match FIFO can delete as many pairs of skip patterns from a cluster as necessary to avoid the
rate match FIFO from overflowing. The rate match FIFO can delete a pair of skip patterns only if the
two 10-bit skip patterns appear in the same clock cycle on the LSByte and MSByte of the 20-bit word.
If the two skip patterns appear straddled on the MSByte of a clock cycle and the LSByte of the next
clock cycle, the rate match FIFO cannot delete the pair of skip patterns.
In the following figure, the first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/
skip pattern in the MSByte of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the
next clock cycle. The rate match FIFO cannot delete the two skip patterns in this skip cluster because
they do not appear in the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the
MSByte of a clock cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate
match FIFO deletes both pairs of /K28.0/ skip patterns (for a total of four skip patterns deleted) from
the second skip cluster to meet the three skip pattern deletion requirement.
The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate
match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or
both, of the 20-bit word.
Figure 2-126: Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion
/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
Dx.y K28.0 Dx.y K28.5 K28.0 K28.0 Dx.y
Dx.y K28.5 K28.0 Dx.y Dx.y
tx_parallel_data[19:10]
rx_parallel_data[9:0]
First Skip Cluster Second Skip Cluster
Two Pairs of Skip
Patterns Deleted
Dx.y K28.5
K28.5
K28.0 K28.0 Dx.ytx_parallel_data[9:0]
Dx.y K28.0 Dx.y
Dx.y
Dx.yrx_parallel_data[19:0]
K28.0
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
The first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the
MSByte of a clock cycle. The rate match FIFO inserts pairs of skip patterns in this skip cluster to meet
the three skip pattern insertion requirement.
UG-01143
2015.05.11
Rate Match FIFO Basic (Double Width) Mode
2-301
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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