User guide

Figure 2-123: Rate Match FIFO Insertion with Three Skip Patterns Required for Insertion
tx_parallel_data
rx_parallel_data
First Skip Cluster
Second Skip Cluster
Three Skip Patterns Inserted
K28.5 K28.0 K28.0 K28.0 K28.5 K28.0 K28.0 Dx.y
K28.5 K28.0 K28.0 K28.0 K28.0 K28.0
K28.5 K28.0 K28.0 K28.0 Dx.y
The following figure shows the deletion of D5 when the upstream transmitter reference clock
frequency is greater than the local receiver reference clock frequency. It asserts rx_std_rmfifo_full
for one parallel clock cycle while the deletion takes place.
Figure 2-124: Rate Match FIFO Becoming Full After Receiving D5
D1 D2 D3 D4 D5 D6 D7 D8
D1 D2 D3 D4 D8 xx xx xxD6
D7
tx_parallel_data
rx_parallel_data
rx_std_rmfifo_full
The following figure shows the insertion of skip symbols when the local receiver reference clock
frequency is greater than the upstream transmitter reference clock frequency. It asserts
rx_std_rmfifo_empty for one parallel clock cycle while the insertion takes place.
Figure 2-125: Rate Match FIFO Becoming Empty After Receiving D3
D1 D2 D3 D4 D5 D6
D1 D2 D3 /K30.7/ D4
D5
tx_parallel_data
rx_parallel_data
rx_std_rmfifo_empty
Rate Match FIFO Basic (Double Width) Mode
1. Select basic (double width) in the RX rate match FIFO mode list.
2. Enter values for the following parameters.
Parameter Value Description
RX rate match insert/delete +ve pattern
(hex)
20 bits of data
specified as a
hexadecimal string
The first 10 bits correspond to the skip
pattern and the last 10 bits correspond
to the control pattern. The skip pattern
must have neutral disparity.
2-300
Rate Match FIFO Basic (Double Width) Mode
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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