User guide

Transceiver Design Flow
Figure 2-2: Transceiver Design Flow
Note: The design examples on the alterawiki page provide useful guidance for developing your own
design. However, the content on the alterawiki page is not guaranteed by Altera.
Generate PHY IP Core
Connect Transceiver Datapath to MAC IP Core or to a Data Generator / Analyzer
Select PLL IP Core
Generate the Altera Transceiver PHY Reset Controller IP Core
or create your own User-Coded Reset Controller
Compile Design
Verify Design Functionality
Generate PLL IP Core
Configure the PHY IP Core
Select PHY IP Core
Configure the PLL IP Core
Connect PHY IP Core to PLL IP Core, Reset Controller, and
connect reconfiguration logic via Avalon-MM interface
Create reconfiguration logic
(if needed)
Make analog parameter settings to I/O pins using the Assignment Editor or updating the Quartus II Settings File
Related Information
http://www.alterawiki.com
Select and Instantiate the PHY IP Core
Select the appropriate PHY IP core to implement your protocol.
Refer to the Arria 10 Transceiver Protocols and PHY IP Support section to decide which PHY IP to select
to implement your protocol.
You can create your Quartus
®
II project first, and then instantiate the various IPs required for your
design. In this case, specify the location to save your IP HDL files. The current version of the PHY IP does
2-2
Transceiver Design Flow
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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