User guide

Figure 2-117: RX Bit Slip in 16-bit Mode
tx_parallel_data = 16'hfcbc
979f cbcf e5e7 f2f3 f979 fcbc
fcbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
00001 00010 00011 00100 00101 00110
Figure 2-118: RX Bit Slip in 20-bit Mode
tx_parallel_data = 20'h3fcbc
3fcbc
rx_std_bitslipboundarysel
rx_bitslip
tx_parallel_data
rx_parallel_data
00001 00010 00011 00100 00101 00110 00111 01000
e5e1f f2f0f f9787 fcbc3 de5e1 ff2f0 7f978 3fcbc
RX Polarity Inversion
Receiver polarity inversion can be enabled in low latency, basic, and basic rate match modes.
To enable the RX polarity inversion feature, select the Enable RX polarity inversion and Enable
rx_polinv port options.
This mode adds rx_polinv. If there is more than one channel in the design, rx_polinv is a bus in which
each bit corresponds to a channel. As long as rx_polinv is asserted, the RX data received has a reverse
polarity.
You can verify this feature by monitoring rx_parallel_data.
Figure 2-119: RX Polarity Inversion
tx_parallel_data
rx_parallel_data
11111100001110111100
11111100001... 00000011110001000011
01
11
11111100001110111100
rx_polinv
rx_patterndetect
rx_syncstatus
RX Bit Reversal
The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word
aligner is available in any mode, bit slip, manual, or synchronous state machine.
To enable this feature, select the Enable RX bit reversal and Enable rx_std_bitrev_ena port options. This
adds rx_std_bitrev_ena. If there is more than one channel in the design, rx_std_bitrev_ena becomes
UG-01143
2015.05.11
RX Polarity Inversion
2-297
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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