User guide

Implementing Protocols in Arria 10
Transceivers
2
2015.05.11
UG-01143
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Transceiver Design IP Blocks
Figure 2-1: Arria 10 Transceiver Design Fundamental Building Blocks
Transceiver
PLL IP Core
Master/Local
Clock
Generation
Block
Avalon-MM Master
Reset Ports
Analog and Digital
Reset Bus
Reconfiguration
Registers
Avalon-MM
Interface
Non-Bonded and
Bonded Clocks
Transceiver PHY IP Core
(1)
Note:
Transceiver
Reset Controller
(2)
Legend:
Altera generated IP block
User created IP block
MAC IP Core /
Data Generator /
Data Analyzer
Parallel Data Bus
Avalon master allows access to Avalon-MM
reconfiguration registers via the Avalon
Memory Mapped interface. It enables PCS,
PMA , and PLL reconfiguration. To access
the reconfiguration registers, implement an
Avalon master in the FPGA fabric. This faciliates
reconfiguration by performing reads and writes
through the Avalon-MM interface.
Transceiver PLL IP core provides a clock source
to clock networks that drive the transceiver
channels. In Arria 10 devices, PLL IP Core
is separate from the transceiver PHY IP core.
Reset controller is used for resetting the
transceiver channels.
This block can be either a MAC IP core, or
a frame generator / analyzer or a
data generator / analyzer.
Transceiver PHY IP core controls the PCS and
PMA configurations and transceiver
channels functions for all communication
protocols.
(1) The Transceiver Native PHY IP core can be one of the supported PHY IP Cores ( For example: Native PHY IP Core/XAUI PHY IP Core, and so on)
(2) You can either design your own reset controller or use the Altera Transceiver PHY Reset Controller IP Core.
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