User guide

Parameters Value
FPGA fabric / Standard TX PCS interface width 32
FPGA fabric / Standard RX PCS interface width 32
Enable 'Standard PCS' low latency mode Off
TX FIFO mode register_fifo
RX FIFO mode register_fifo
Enable tx_std_pcfifo_full port Off
Enable tx_std_pcfifo_empty port Off
Enable rx_std_pcfifo_full port Off
Enable rx_std_pcfifo_empty port Off
TX byte serializer mode
Serialize x2
RX byte deserializer mode
Deserialize x2
Enable TX 8B/10B encoder On
Enable TX 8B/10B disparity control Off
Enable RX 8B/10B decoder On
RX rate match FIFO mode Disabled
RX rate match insert / delete -ve pattern (hex)
0x00000000
RX rate match insert / delete +ve pattern (hex)
0x00000000
Enable rx_std_rmfifo_full port Off
Enable rx_std_rmfifo_empty port Off
PCI Express Gen3 rate match FIFO mode Bypass
Enable TX bit slip
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
Enable tx_std_bitslipboundarysel port
Off (CPRI Auto configuration)
On (CPRI Manual configuration)
RX word aligner mode
deterministic latency (CPRI Auto configuration)
manual (FPGA fabric controlled) (CPRI Manual
configuration)
RX word aligner pattern length 10
RX word aligner pattern (hex)
0x000000000000017c
UG-01143
2015.05.11
Native PHY IP Parameter Settings for CPRI
2-277
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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