User guide
IP Core File Locations...................................................................................................................2-75
Interlaken....................................................................................................................................................2-76
Metaframe Format and Framing Layer Control Word............................................................2-78
Interlaken Configuration Clocking and Bonding..................................................................... 2-79
How to Implement Interlaken in Arria 10 Transceivers..........................................................2-86
Design Example..............................................................................................................................2-90
Native PHY IP Parameter Settings for Interlaken.....................................................................2-90
Ethernet.......................................................................................................................................................2-97
Gigabit Ethernet (GbE) and GbE with IEEE 1588v2................................................................ 2-97
10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants.........2-110
10GBASE-KR PHY IP Core ......................................................................................................2-125
1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core...............................................................2-163
XAUI PHY IP Core..................................................................................................................... 2-211
Acronyms......................................................................................................................................2-227
PCI Express (PIPE)..................................................................................................................................2-228
Transceiver Channel Datapath for PIPE..................................................................................2-229
Supported PIPE Features............................................................................................................2-229
How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes.....................................2-239
How to Implement PCI Express (PIPE) in Arria 10 Transceivers........................................2-245
Native PHY IP Parameter Settings for PIPE ...........................................................................2-246
Native PHY IP Ports for PIPE....................................................................................................2-254
How to Place Channels for PIPE Configurations................................................................... 2-261
PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate.................................2-265
Design Example............................................................................................................................2-267
CPRI...........................................................................................................................................................2-268
Transceiver Channel Datapath and Clocking for CPRI.........................................................2-268
Supported Features for CPRI ....................................................................................................2-270
Word Aligner in Manual Mode for CPRI................................................................................ 2-271
How to Implement CPRI in Arria 10 Transceivers................................................................ 2-272
Native PHY IP Parameter Settings for CPRI...........................................................................2-275
Other Protocols........................................................................................................................................2-279
Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS.........................................................................................................................2-279
Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard
PCS...........................................................................................................................................2-290
Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels....2-313
How to Implement PCS Direct Transceiver Configuration Rule.....................................................2-321
Simulating the Transceiver Native PHY IP Core................................................................................2-322
NativeLink Simulation Flow...................................................................................................... 2-323
Custom Simulation Flow............................................................................................................2-328
PLLs and Clock Networks................................................................................... 3-1
PLLs................................................................................................................................................................3-3
ATX PLL............................................................................................................................................3-3
fPLL..................................................................................................................................................3-13
CMU PLL........................................................................................................................................3-21
Input Reference Clock Sources................................................................................................................3-27
Dedicated Reference Clock Pins..................................................................................................3-28
Arria 10 Transceiver PHY Overview
TOC-3
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