User guide

Port Direction Clock Domain Description
pipe_rx_sync_hdr[1:0] Out rx_coreclkin
For Gen3, indicates whether the 130-
bit block being transmitted is a Data
or Control Ordered Set Block. The
following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set block
This value is read when pipe_rx_blk_
start = 4'b0001. Refer to Section
4.2.2.1. Lane Level Encoding in the PCI
Express Base Specification, Rev. 3.0 for
a detailed explanation of data
transmission and reception using
128b/130b encoding and decoding.
pipe_rx_blk_start Out rx_coreclkin
For Gen3, specifies the start block byte
location for RX data in the 128-bit
block data. Used when the interface
between the PCS and PHY-MAC
(FPGA Core) is 32 bits. Not used for
Gen1 and Gen2 data rates.
Active High
pipe_rx_data_valid Out rx_coreclkin
For Gen3, this signal is deasserted by
the PHY to instruct the MAC to
ignore rx_parallel_data for current
clock cycle. A value of 1'b1 indicates
the MAC should use the data. A value
of 1'b0 indicates the MAC should not
use the data.
Active High
pipe_rx_valid Out rx_coreclkin
Asserted when RX data and control
are valid.
pipe_phy_status Out rx_coreclkin
Signal used to communicate
completion of several PHY requests.
Active High
pipe_rx_elecidle Out Asynchronous
When asserted, the receiver has
detected an electrical idle.
Active High
2-260
Native PHY IP Ports for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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