User guide

Port Direction Clock Domain Description
pipe_rate[1:0] In Asynchronous
The 2-bit encodings defined in the
following list:
2'b00: Gen1 rate (2.5 Gbps)
2'b01: Gen2 rate (5.0 Gbps)
2'b1x: Gen3 rate (8.0 Gbps)
pipe_sw_done In N/A
Signal from the Master clock
generation buffer, indicating that the
rate switch has completed. Use this
signal for bonding mode only.
For non-bonded applications, this
signal is internally connected to the
local CGB.
pipe_tx_data_valid In tx_coreclkin
For Gen3, this signal is deasserted by
the MAC to instruct the PHY to
ignore tx_parallel_data for current
clock cycle. A value of 1'b1 indicates
the PHY should use the data. A value
of 0 indicates the PHY should not use
the data.
Active High
PIPE Output to PHY - MAC Layer
rx_parallel_data[31:0],
[15:0], or [7:0]
Out rx_coreclkin
The RX parallel data driven to the
MAC.
For Gen1 this can be 8 or 16 bits. For
Gen2 this is 16 bits only. For Gen3 this
is 32 bits.
rx_datak[3:0], [1:0], or
[0]
Out rx_coreclkin
The data and control indicator.
For Gen1 or Gen2, when 0, indicates
that rx_parallel_data is data, when
1, indicates that rx_parallel_data is
control.
For Gen3, Bit[0] corresponds to rx_
parallel_data[7:0], Bit[1]
corresponds to rx_parallel_
data[15:8], and so on.
UG-01143
2015.05.11
Native PHY IP Ports for PIPE
2-259
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
Send Feedback