User guide

Note: 1. The GT channels can also operate in PCS Direct configuration for data rates from 611 Mbps to
28.3 Gbps. The PCS Direct datapath that bypasses all PCS blocks is the primary configuration
used to support GT data rates from 17.4 Gbps to 28.3 Gbps.
2. The transmitter minimum operational data rate is 611 Mbps. For transmitter data rates less
than 611 Mbps, oversampling must be applied at the transmitter.
3. The receiver minimum operational data rate is 1.0 Gbps. For receiver data rates less than 1.0
Gbps, oversampling must be applied at the receiver.
Transceiver Phase-Locked Loops
Each transceiver channel in Arria 10 devices has direct access to three types of high performance PLLs:
• Advanced Transmit (ATX) PLL
• Fractional PLL (fPLL)
• Channel PLL / Clock Multiplier Unit (CMU) PLL.
These transceiver PLLs along with the Master or Local Clock Generation Blocks (CGB) drive the
transceiver channels.
Related Information
PLLs on page 3-3
For more information on transceiver PLLs in Arria 10 devices.
Advanced Transmit (ATX) PLL
An advanced transmit (ATX ) PLL is a high performance PLL. It supports both integer frequency
synthesis and coarse resolution fractional frequency synthesis. The ATX PLL is the transceiver channel’s
primary transmit PLL. It can operate over the full range of supported data rates required for high data rate
applications.
Related Information
• ATX PLL on page 3-3
For more information on ATX PLL.
• ATX PLL IP Core on page 3-6
For details on implementing the ATX PLL IP.
Fractional PLL (fPLL)
A fractional PLL (fPLL) is an alternate transmit PLL used for generating lower clock frequencies for low
data rate applications. fPLLs support both integer frequency synthesis and fine resolution fractional
frequency synthesis. Unlike the ATX PLL, the fPLL can also be used to synthesize frequencies that can
drive the core through the FPGA fabric clock networks.
Related Information
• fPLL on page 3-13
For more information on fPLL.
• fPLL IP Core on page 3-15
For details on implementing the fPLL IP.
UG-01143
2015.05.11
Transceiver Phase-Locked Loops
1-23
Arria 10 Transceiver PHY Overview
Altera Corporation
Send Feedback