User guide

Port Direction Clock Domain Description
pipe_tx_deemph In Asynchronous
Transmit de-emphasis selection. In
PCI Express Gen2 (5 Gbps) mode it
selects the transmitter de-emphasis:
1'b0: –6 dB
1'b1: –3.5 dB
pipe_g3_txdeemph[17:0] In Asynchronous
For Gen3, selects the transmitter de-
emphasis. The 18 bits specify the
following coefficients:
[5:0]: C-1
[11:6]: C0
[17:12]: C+1
In Gen3 capable designs, the TX de-
emphasis for Gen2 data rate is always -
6 dB. The TX de-emphasis for Gen1
data rate is always -3.5 dB.
Refer to section 6.6 of Intel PHY
Interface for PCI Express (PIPE)
Architecture for more information.
pipe_g3_rxpresethint
In Asynchronous
Provides the RX preset hint for the
receiver.
pipe_rx_eidlein-
fersel[2:0]
In Asynchronous
When asserted high, the electrical idle
state is inferred instead of being
identified using analog circuitry to
detect a device at the other end of the
link. The following encodings are
defined:
3'b0xx: Electrical Idle Inference not
required in current LTSSM state
3'b100: Absence of COM/SKP OS in
128 ms
3'b101: Absence of TS1/TS2 OS in
1280 UI interval for Gen1 or Gen2
3'b110: Absence of Electrical Idle Exit
in 2000 UI interval for Gen1 and
16000 UI interval for Gen2
3'b111: Absence of Electrical Idle exit
in 128 ms window for Gen1
Note:
Recommended to
implement Receiver
Electrical Idle Inference
(EII) in FPGA fabric
2-258
Native PHY IP Ports for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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