User guide

Port Direction Clock Domain Description
pipe_tx_compliance In tx_coreclkin
Asserted for one cycle to set the
running disparity to negative. Used
when transmitting the compliance
pattern. Refer to section 6.11 of Intel
PHY Interface for PCI Express (PIPE)
Architecture for more information.
Active High
pipe_rx_polarity In Asynchronous
When 1'b1, instructs the PHY layer to
invert the polarity on the received
data.
Active High
pipe_powerdown[1:0] In tx_coreclkin
Requests the PHY to change its power
state to the specified state. The Power
States are encoded as follows:
2'b00: P0 - Normal operation
2'b01: P0s - Low recovery time, power
saving state
2'b10: P1 - Longer recovery time,
lower power state
2'b11: P2 - Lowest power state
pipe_tx_margin[2:0] In tx_coreclkin
Transmit V
OD
margin selection. The
PHY-MAC sets the value for this
signal based on the value from the
Link Control 2 Register. The following
encodings are defined:
3'b000: Normal operating range
3'b001: Full swing: 800 - 1200 mV;
Half swing: 400 - 700 mV
3'b010:-3'b011: Reserved
3'b100-3'b111: Full swing: 200 -
400mV; Half swing: 100 - 200 mV else
reserved
pipe_tx_swing
In tx_coreclkin
Indicates whether the transceiver is
using Full swing or Half swing voltage
as defined by the pipe_tx_margin
1'b0-Full swing
1'b1-Half swing
UG-01143
2015.05.11
Native PHY IP Ports for PIPE
2-257
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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