User guide

Port Direction Clock Domain Description
pipe_tx_sync_hdr[1:0] In tx_coreclkin
For Gen3, indicates whether the 130-
bit block transmitted is a Data or
Control Ordered Set Block.
The following encodings are defined:
2'b10: Data block
2'b01: Control Ordered Set Block
This value is read when pipe_tx_blk_
start = 1b'1
Refer to Lane Level Encoding in the
PCI Express Base Specification, Rev. 3.0
for a detailed explanation of data
transmission and reception using
128b/130b encoding and decoding.
Not used for Gen1 and Gen2 data
rates.
Active High
pipe_tx_blk_start
In tx_coreclkin
For Gen3, specifies the start block byte
location for TX data in the 128-bit
block data. Used when the interface
between the PCS and PHY-MAC
(FPGA Core) is 32 bits.
Not used for Gen1 and Gen2 data
rates.
Active High
pipe_tx_elecidle In Asynchronous
Forces the transmit output to electrical
idle. Refer to Intel PHY Interface for
PCI Express (PIPE) for timing
diagrams.
Active High
pipe_tx_detectrx_
loopback
In tx_coreclkin
Instructs the PHY to start a receive
detection operation. After power-up,
asserting this signal starts a loopback
operation. Refer to section 6.4 of Intel
PHY Interface for PCI Express (PIPE)
for a timing diagram.
Active High
2-256
Native PHY IP Ports for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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